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ATmega128
TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Extended
Timer/Counter
Bit
7
6
5
4
3
2
1
0
Interrupt Flag Register
–
–
ICF3
OCF3A
OCF3B
TOV3
OCF3C
OCF1C
ETIFR
– ETIFR
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
? Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIFR is written.
? Bit 5 – ICF3: Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. W hen the Input Capture Register
(ICR3) is set by the W GM3:0 to be used as the TOP value, the ICF3 flag is set when the counter
reaches the TOP value.
ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed. Alterna-
tively, ICF3 can be cleared by writing a logic one to its bit location.
? Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register A (OCR3A).
Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag.
OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector is exe-
cuted. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.
? Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register B (OCR3B).
Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag.
OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector is exe-
cuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.
? Bit 2 – TOV3: Timer/Counter3, Overflow Flag
The setting of this flag is dependent of the W GM3:0 bits setting. In normal and CTC modes, the
TOV3 flag is set when the timer overflows. Refer to Table 52 on page 104 for the TOV3 flag
behavior when using another W GM3:0 bit setting.
TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector is executed.
Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
? Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register C (OCR3C).
Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag.
OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector is exe-
cuted. Alternatively, OCF3C can be cleared by writing a logic one to its bit location.
? Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register C (OCR1C).
141
2467X–AVR–06/11
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